Semiconductor devices can be formed on bulk semiconductor substrates or semiconductor-on-insulator (SOI) structures. Compared to devices formed on bulk semiconductor substrates (bulk devices), devices formed on SOI structures (SOI devices) generally have lower parasitic capacitances, higher switching speeds, lower power consumption, a higher circuit packing density, and a higher yield.
A conventional SOI device, such as a transistor 100 formed on an SOI structure 102, is shown in FIG. 1. SOI structure 102 includes a semiconductor substrate 104, an insulating layer 106 on semiconductor substrate 104, and a semiconductor film 108 on insulating layer 106. Semiconductor substrate 104 may comprise silicon. Insulating layer 106 may comprise buried silicon oxide. Semiconductor film 108 may comprise a silicon film, a silicon germanium (SiGe) film, or any other semiconductor filme, and may be doped with n-type or p-type impurities. Transistor 100 includes a source 110 and a drain 112 formed as diffusion regions in semiconductor film 108. A channel 114 is defined as a portion of semiconductor film 108 between source 110 and drain 112. Transistor 100 further includes a layer of gate insulator 116 formed over channel 114 and a gate electrode 118 formed on gate insulator 116.
Memory devices such as static random access memory (SRAM) devices have been formed on SOI structures to achieve better performance than SRAM devices formed on bulk semiconductor substrates. Conventional SOI SRAM devices may include transistors similar to transistor 100 and other devices such as capacitors and/or resistors.
FIGS. 2A-2E show an example of a conventional SOI SRAM device 200. FIG. 2A is a plan view of SOI SRAM device 200. As shown in FIG. 2A, SOI SRAM device 200 includes a memory array 202. Memory array 202 is divided into four memory blocks 204. An address decoder 206 decodes address inputs (not shown) to SRAM device 200, provides word line address information to a global word line 208, and provides bit line address information to memory blocks 204.
FIG. 2B shows the structure of each memory block 204. As shown in FIG. 2B, each memory block 204 includes a plurality of smaller memory arrays, or memory banks, 210. Each memory bank 210 corresponds to a local word line decoder 212, a bit line decoder 214, and one or more bit line sense amplifier (BL-SA) circuits 216 (only one of which is shown for each memory bank 210). Local word line decoders 212 are coupled to global word line 208, which is parallel to word lines (not shown) of memory banks 210, to receive the word line address information. Bit line decoders 214 are coupled to address decoder 206 to receive the bit line address information through a local bit line address line 215. BL-SA circuits 216 provide data paths between memory banks 210 and external circuits (not shown).
FIG. 2C shows the structure of each memory bank 210. As shown in FIG. 2C, each memory bank 210 includes an array of memory cells 218 arranged in a plurality of rows each corresponding to a pair of bit lines 220 (2201, 2202, 2203, . . .) and 222 (2221, 2222, 2223, . . .) and a plurality of columns each corresponding to a word line 224 (2241, 2242, 2243, . . .). Bit lines 220 and 222 are connected to a corresponding bit line decoder 214 and at least one corresponding BL-SA circuit 216. Word lines 224 are connected to a corresponding local word line decoder 212. Each memory cell 218 may comprise one or more transistors similar to transistor 100 of FIG. 1. The structure of memory cells 218 is well-known to one skilled in the art and is not illustrated in detail in FIG. 2C.
The performance of conventional SOI SRAM devices is limited by so-called floating-body effects. For example, in an SOI SRAM device including transistor 100, semiconductor film 108, which constitutes a body region of transistor 100, is electrically isolated. Accordingly, the potential of semiconductor film 108 is floating and may be modulated through charging or discharging of the charges in semiconductor film 108. For example, semiconductor film 108 may be charged or discharged through impact ionization currents, junction leakage currents, and/or gate-induced drain leakage current. The charge distribution in semiconductor film 108 is also substantially influenced by a charge distribution in semiconductor substrate 104. Due to such floating-body effects, a conventional SOI SRAM device requires a higher minimum operating voltage Vmin.
According to conventional technologies, to reduce the floating-body effects and to decrease the minimum required operating voltage Vmin, there are generally provided substrate contacts in the peripheral regions of an SOI SRAM device. For example, as shown in FIG. 2A, SOI SRAM device 200 includes a plurality of substrate contacts 230 provided in the peripheral regions thereof. FIG. 2D illustrates a cross-sectional view of one substrate contact 230 along line A-A′ of FIG. 2A. As shown in FIG. 2D, SOI SRAM device 200 is formed on an SOI structure 232 including a semiconductor substrate 234, an insulating layer 236 on semiconductor substrate 234, and a semiconductor film 238 on insulating layer 236. A plurality of device isolation regions 240 (only one of which is shown in FIG. 2D) are formed in semiconductor film 238 for providing electrical isolation between different portions of SOI SRAM device 200. Substrate contact 230 may comprise a metal plug provided in a substrate contact hole (not numbered) through both device isolation region 240 and insulating layer 236 and is connected to a heavily doped diffusion region 242 formed in semiconductor substrate 234. Diffusion region 242 has the same conductivity type as semiconductor substrate 234. For example, if semiconductor substrate 234 is p-type, then diffusion region 242 is p+-type. Thus, semiconductor substrate 234 may be properly biased by providing a bias to substrate contact 230, such as by connection to a ground potential, to reduce the floating-body effect of SOI SRAM device 200. As a result, memory device 200 as shown in FIGS. 2A-2D has a reduced minimum operating voltage Vmin as compared to a device without substrate contacts. For example, the minimum operating voltage Vmin of memory device 200 may be lower than that of a device without substrate contacts by 0.1V.
FIG. 2A shows substrate contacts 230 to be in a square shape. The substrate contacts may also comprise rectangular contact bars, such as substrate contacts 230′ shown in FIG. 2E.